Mnoho zpozdeni u embedded hardware projektu nezacina ve firmware. Zacina ve chvili, kdy se tym snazi nacpat prilis mnoho rozhrani, prilis vysokou hustotu a prilis mnoho mechanickych omezeni do bezneho stackupu, ktery uz je na hrane.
U prumyslovych gateway, ridicich modulu a kompaktni komunikacni techniky se problem obvykle ukaze ve chvili, kdy pribyde 0.5 mm BGA, DDR, radio, shielding a husty connector. V ten moment uz HDI neni luxus, ale prakticky zpusob, jak se vyhnout dalsimu layout spinu a dalsimu zpozdeni EVT.
Why HDI PCB Matters
HDI dava smysl tehdy, kdyz se soucasne stretnou elektricka hustota, mechanicky obrys a cil spolehlivosti. Pokud standardni deska funguje uz jen za cenu delsich tras, prilis mnoha prechodu mezi layer a nuceneho presunu connectoru, mela by se HDI seriozne nacenit.
| Product type | Typical HDI trigger | Common stackup starting point | Main sourcing risk |
|---|---|---|---|
| Embedded SOM carrier board | 0.5 mm BGA, DDR routing, limited outline | 6L or 8L with 1-N-1 microvia | Escapes work in prototype but yield drops in volume |
| Industrial gateway | Ethernet, CAN, RS-485, wireless module, isolated power | 6L with selective microvia | EMI and creepage constraints compete for space |
| Compact HMI controller | Display connector density, processor + PMIC crowding | 6L HDI | Assembly warpage and rework difficulty |
| Radio or telecom module | Controlled impedance, shielding, dense RF + digital coexistence | 6L or 8L HDI | Impedance drift and stackup inconsistency |
| Edge AI or vision board | LPDDR, CSI/DSI, multiple regulators, thermal crowding | 8L HDI | Prototype passes, mass production gets copper balance issues |
| Rugged embedded I/O module | Small form factor plus harsh-environment test margins | 4L or 6L with microvia | Buyer under-specifies test plan and documentation |
"The expensive mistake is not choosing HDI too early. The expensive mistake is staying with a conventional stackup one revision too long, then paying for a rushed redesign after the enclosure, cable set, and firmware architecture are already frozen."
— Hommer Zhao, Engineering Director at FlexiPCB
Embedded Systems vs Communication Equipment
U embedded desek je problem casto integrace. U komunikacnich desek je problem casto rezerva: impedance, return path, shielding, loss a opakovatelnost mezi vyrobnimi sarzemi. Stejna microvia tak resi podle produktu jiny typ rizika.
See our HDI flex PCB service page, impedance control guide, and flex PCB prototype guide for supporting detail.
Stackup, Cost, and Lead Time
Nestaci rici jen “chceme HDI board”. Dulezite je zvolit spravnou uroven HDI. 6L nebo 8L 1-N-1 pokryje mnoho realnych navrhu. 2-N-2 nebo filled via-in-pad by se mely pouzit jen tehdy, kdyz to skutecne dokazuje routing.
| HDI build option | Typical use case | Relative fabrication cost | Relative lead time | Procurement comment |
|---|---|---|---|---|
| 4L with selective microvia | Compact industrial controller | 1.2x-1.5x | +2-4 days | Good first HDI step when density is moderate |
| 6L 1-N-1 HDI | Embedded compute, gateway, HMI | 1.5x-2.2x | +4-7 days | Most common balance of density and manufacturability |
| 8L 1-N-1 HDI | Dense processor plus memory plus comms | 2.0x-3.0x | +5-10 days | Strong option when routing density is real, not speculative |
| 8L 2-N-2 HDI | Telecom, RF-digital mixed boards, high escape demand | 2.8x-4.0x | +8-14 days | Only justify when layout proof shows 1-N-1 is insufficient |
| Via-in-pad + filled microvia | Ultra-dense BGA, shortest path, thermal pad escape | 3.0x-4.5x | +8-14 days | Excellent technically, expensive if overused |
"A buyer can save 20% on bare board price and still lose the program if the chosen stackup adds one more prototype loop, two more weeks of validation, and a redesign of the shielding or connector geometry."
— Hommer Zhao, Engineering Director at FlexiPCB
RFQ Checklist
Uzitecna nabidka nevznikne tim, ze poslete jen Gerber. Vznika tehdy, kdyz dodate i technicky zamer: outline, kriticke package, cilovy stackup, mnozstvi, pozadavky na impedance a skutecne provozni prostredi.
- board outline and mechanical drawing
- Gerber or ODB++ data plus drill files
- BOM or at minimum the key fine-pitch packages, connectors, and RF parts
- quantity split: prototype quantity, pilot run, and annual demand
- operating environment, service life, and target lead time
- compliance target such as RoHS, UL, or customer specification
Prototype vs Production Risk
Prvni HDI prototype dokazuje jen to, ze desku lze jednou vyrobit. Nedokazuje, ze v seriove vyrobe zustane stejna rovinnost, via filling, impedance a stabilita montaze.
"If you want prototype results to predict mass production, the fabricator must know your intended production volume, test level, and qualification target at the quotation stage. Otherwise the prototype is optimized for speed, while production is optimized for repeatability, and the two do not match."
— Hommer Zhao, Engineering Director at FlexiPCB
Review assembly impact together with your flex assembly strategy and detailed routing constraints such as those in our component placement guide.
Qualification and Testing
Uz ve fazi RFQ urcete, jake dukazy potrebujete: impedance coupon, microsection, kvalitu plating, traceability, potvrzeni surface finish a pripadne environmental testing. Pokud produkt miri do tvrdeho prumysloveho prostredi, musi to byt napsane od zacatku.
Use IPC, embedded systems, and telecommunications equipment references as part of the supplier review discussion.
FAQ
Kdy by mela embedded deska prejit z bezne PCB na HDI?
Kdyz BGA escape, DDR fan-out, huste connector nebo limity enclosure nuti delat kompromisy v signal, EMC nebo manufacturability. Pokud 6-layer deska funguje jen s prilis mnoha objizdkami, je cas proverit 1-N-1.
Staci 1-N-1 pro vetsinu komunikacnich zarizeni?
U mnoha gateway, controller a kompaktni communication module ano. 6L nebo 8L 1-N-1 casto nabizi nejlepsi pomer hustoty, ceny a lead time. Narocnejsi RF navrhy potrebuji dalsi validaci.
Co ma buyer zahrnout do RFQ pro HDI PCB?
Drawing, Gerber nebo ODB++, BOM nebo seznam kritickych package, mnozstvi, target lead time, prostredi, impedance target a compliance target. Bez toho muze dodavatel dat cenu, ale ne pevne technicke doporuceni.
Proc nekdy HDI prototype projde, ale serie ma problemy?
Protoze prototype je casto optimalizovana na rychlost, zatimco serie vyzaduje material control, registration, copper balance, via filling a assembly flatness. Pokud neni seriovy zamer stanoven vcas, vysledky se rozjedou.
Co by mel dodavatel vratit po review HDI projektu?
Minimalne stackup recommendation, DFM comments, lead-time options, tooling assumptions, test suggestions a body, ktere mohou zasahnout yield pri vyssim objemu.
Next Step
Poslete drawing nebo Gerber, BOM nebo seznam klicovych soucastek, mnozstvi prototype a production, provozni prostredi, target lead time a compliance target. Vratime DFM review, stackup recommendation, rizika prototype versus production a nabidku s variantami lead time. Zacnete pres quote nebo contact.
